A GOLD code is formed by adding two m sequences PN 1 and PN 2, which are in synchronism with a clock signal CLK, modulo 2 by means of an exclusive logical sum (hereinbelow abbreviated to EOR) gate, as indicated in FIG. 8 (e.g., Japanese Application No. 61-163088, which corresponds to U.S. Ser. No. 070 491 filed July 7, 1987). In FIG. 8, PNG 1 and PNG 2 are m sequence generators and EOR indicates an exclusive logical sum gate.
As an m sequence generator in the form of an IC there is known a construction e.g. as indicated in FIG. 9. In FIG. 9 G.sub.1 .about.G.sub.n are steering gates setting the initial value for shift registers and switching the operation of the shift registers; SR.sub.1 .about.SR.sub.n are flipflops constituting the shift registers; L.sub.1 .about.L.sub.6 are latch circuits; MPX is a multiplexer; AND.sub.0 .about.AND.sub.n are AND circuits; DE-MPX is a demultiplexer; and INV.sub.1, INV.sub.2 are inverters. Further CLK represents a supplied clock signal; STB an m sequence generation initializing signal; CS a chip select signal; LE a latch enable signal; DAT 0 .about.n data; SEL 0 .about.1 data select signals; FB 0 a feedback input terminal; FB 1 an input terminal to the first stage steering gate; CAS an output for connecting the m sequence generators in cascade; FB 2 a three state output; PN a sequence output; and e,ovs/FBCNT/ a control input terminal of the multiplexer MPX having the three state output.
However there are known neither circuits stated above and indicated in FIG. 9 nor prior art m sequence generators having a built-in GOLD code generating circuit. Consequently, when a GOLD code was to be generated, it was necessary to connect an external circuit EX therewith, as indicated in FIG. 10. In FIG. 10 PNG 1 and PNG 2 are m sequence generators; EOR represents an exclusive logical sum gate; and D-FF represents a D-type flipflop. FIG. 11 shows waveforms in different parts of the circuit indicated in FIG. 10. Even if PNG 1 and PNG 2 are constructed by a same kind of ICs, since there are fluctuations in transmission delay time from the clock input CLK to the m sequence outputs PN 1 and PN 2, in the case where the output of the EOR gate is used as a GOLD code,the GOLD code is obtained usually by synchronizing PNG 1 and PNG 2 with a same clock, after the output of the EOR gate has been stabilized in a desired state.
For this reason, as indicated in FIG. 12, the GOLD code is outputted with a delay of 1 chip (1 period of clock) with respect to the m sequences PN 1 and PN 2. Such a phase delay of the GOLD code with respect to the n sequences as indicated in FIG. 10 was an inevitable problem, as far as the GOLD code was generated by an external circuit EX.